1. Field of the Invention
The present invention relates to a method for driving a plasma display panel (PDP) used as a flat plasma display device such as a television, computer or a like, its driving circuit and a plasma display device having the driving circuit and more particularly to the method for an alternating current (AC) driving surface-discharge type plasma display, its driving circuit and the plasma display device provided with the driving circuit of such plasma display.
The present application claims priority of Japanese Patent Application No. 2000-372118 filed on Dec. 6,2000, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 14 is a schematic exploded perspective view showing configurations of a conventional AC driving surface-discharge type PDP 1 disclosed in, for examples Japanese Patent No. 3036496 or Japanese Laid-open Patent Application No. Hei 11-202831. FIG. 15 is an enlarged cross-sectional view showing one display cell of the conventional PDP 1. The display cell is a minimum unit making up a display screen. It should be noted that FIG. 15 shows a view obtained by cutting the PDP 1 illustrated in FIG. 14 in a longitudinal direction with its components being not resolved and obtained by viewing its right cross section.
In the PDP 1 shown in FIGS. 14 and 15, a plurality of stripe-shaped scanning electrodes 3 (31-3n) (may hereinafter referred to as the scanning electrode 3 (31-3n)) and stripe-shaped sustaining electrodes 41-4n may hereinafter referred to as the sustaining electrode 4 (41-4n)) each being constructed of a transparent conductive thin film made of Indium Tin Oxide (ITO), tin oxide or a like, is formed at established intervals alternately on an under surface of a front insulating substrate 2 made of glass in a row direction (in a right to left direction in FIG. 14) and, in order to decrease a resistance value of the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n) each having low conductivity, a plurality of trace electrodes 5 and 6 each being made up of a metal film such as a silver thick film or a like is formed on end side of an under surface of the scanning electrode 3 (31-3n) and the sustaining electrode 4 (41-4n) The under surface of the scanning electrode 3 (31-3n) and the sustaining electrode 4 (41-4n) and an under surface of the front insulating substrate 2 on which the scanning electrodes 3 and the sustaining electrode 4 (41-4n) are not formed, is coated with a transparent dielectric layer 7 and an under surface of the dielectric layer 7 is coated with a protection layer 8 made from magnesium oxide which is used to protect the dielectric layer 7 from ion bombardment at a time of discharging.
On the other hand, a plurality of stripe-formed data electrodes 101-10m(may hereinafter referred to as the data electrode 10 (101-10m)) made up of silver films or a like is formed on an upper surface of a rear insulating substrate 9 made from glass in a column direction (in a left to right direction in FIG. 14), that is, in a direction orthogonal to a direction in which the scanning electrode 3 (31-3n) and the sustaining electrode 4 (41-4n) are formed and an upper surface of the data electrode 10 (101-10m) and the upper surface of the rear insulating substrate 9 on which the data electrode 10 (101-10m) are not formed is coated with a dielectric layer 11. Moreover, stripe-shaped ribs (partitioning walls) 12 (hereinafter referred to as the rib 12) used to partition the display cell are formed on an upper surface of the dielectric layer 11 except an upper portion of the data electrode 10 (101-10m) and three kinds of fluorescent layers 13R, 13G, and 13B each converting ultra-violet rays produced by discharge of discharging gas into visible light having three primary colors including a red (R) color, green (G) color, and blue (B) color are formed on the upper surface of the di electric layer 11 existing in an upper portion of the data electrode 10 (101-10m) and on sides of the rib 12. The fluorescent layers 13R, 13G, and 13B are formed in order of the fluorescent layer 13R, fluorescent layer 13G and fluorescent layer 13, in a row direction sequentially and repeatedly, and fluorescent layers 13R, 13G, and 13B used to convert ultra-violet rays into visible light having a same color are formed successively in a column direction. A discharging gas space 14 is secured which is formed by an under surface of the protection layer 8, by an upper surface of each of the fluorescent layers 13R, 13G, and 13B, and by side walls of two ribs 12 being adjacent to each other. The discharging gas space 14 is filled with a discharging gas containing helium, neon or xenon or its mixed gas. A region made up of the scanning electrode 3 (31-3n), the sustaining electrode 4 (41-4n), the trace electrodes 5 and 6, the data electrode 10 (101-10m), the fluorescent layer 13R, 13G, and 13B, and the discharging gas space 14 serves as the display cell described above.
FIG. 16 is a schematic block diagram showing an example of configurations of a driving circuit of the conventional AC driving surface-discharge type PDP 1 of FIG. 14. In the PDP 1 shown in FIG. 16, n pieces (xe2x80x9cnxe2x80x9d is a natural number) of the scanning electrodes 31 to 3n and n pieces (xe2x80x9cnxe2x80x9d is a natural number) of the sustaining electrodes 41 to 4n are formed at established intervals in a row direction and m pieces (xe2x80x9cmxe2x80x9d is a natural number) of the data electrodes 101 to 10m are formed at established intervals in a column direction and the number of the display cells on an entire display screen is (nxc3x97m) pieces.
The driving circuit of the PDP 1, as shown in FIG. 16, chiefly includes a driving power source 21, a controller 22, a scanning driver 23, a scanning pulse driver 24, a sustaining driver 25, and a data driver 26. The driving power source 21 produces a logic voltage Vdd of 5 Volts and, at a same time, a data voltage Vd of about 70 Volts, and a sustaining voltage Vs of about 180 Volts and also generates, based on the sustaining voltage Vs, a priming voltage VP of about 400 Volts, a scanning base voltage VbW of about 100 Volts and a bias voltage Vsw of about 195 Volts, and feeds the logic voltage Vdd to the controller 22, the data voltage Vd to the data driver 26, the sustaining voltage Vs to the scanning driver 23 and the sustaining driver 25, the priming voltage VP and scanning base voltage Vbw to the scanning driver 23 and the bias voltage Vsw to the sustaining driver 25.
The controller 22 produces, based on a video signal Sv fed from an outside, scanning driver control signals SSCD1 to SSCD6, scanning pulse driver control signals SSPD11 to SSPDin and SSPD21 to SSPD2n, sustaining driver control signals SSUD1 to SSUD3, data driver control signals SDD11 to SDD1m and SDD21 to SDD2m and then feeds the scanning driver control signals SSCD1 to SSCD6 to the scanning driver 23, the scanning pulse driver control signals SSPD11 to SSPD1n and SSPD21 to SSPD2 to the scanning pulse driver 24, the sustaining driver control signals SSUD1, to SSUD3 to the sustaining driver 25, the data driver control signals SDD11 to SDD1m and SDD21 to SDD2m to the data driver 26.
The scanning driver 23, as shown in FIG. 17, includes switches 231 to 236. One terminal of the switch 231 is supplied with the priming voltage Vp and the other terminal of the switch 231 is connected to a positive line 27. One terminal of the switch 232 is supplied with the sustaining voltage Vs and the other terminal of the switch 232 is connected to the positive line 27. One terminal of the switch 233 is connected to a negative line 28 and the other terminal of the switch 233 is connected to a ground. One terminal of the switch 234 is supplied with the scanning base voltage VbW and the other terminal of the switch 234 is connected to the negative line 28. One terminal of the switch 235 is connected to the positive line 27 and the other terminal of the switch 235 is connected to a ground. One terminal of the switch 236 is connected to the negative line 28 and the other terminal of the switch 236 is connected to a ground. Each of the switches 231 to 236 is turned ON/OFF, based on the scanning driver control signals SSCD1 to SSCD6, and applies voltages each having a predetermined waveform through the positive line 27 and negative line 28 to the scanning pulse driver 24.
The scanning pulse driver 24, as shown in FIG. 17, includes n pieces of switches 2411 to 241n, n pieces of switches 2421 to 242n, n pieces of diodes 2431 to 243n and n pieces of diodes 2441 to 244n. Each of the diodes 2431 to 243n is connected in parallel to both ends of each of corresponding switches 2411 to 241n. Each of the diodes 2441 to 244n is connected in parallel to both ends of each of corresponding switches 2421 to 242n. The switch 2411 is daisy-chained to the switch 2421. The switch 2412 is daisy-chained to the switch 2422. The switch 2413 is daisy-chained to the switch 2423. Similarly, the switch 241n is daisy-chained to the switch 242n. The switches 2411 to 241n are connected to the negative line 28 with all of one terminal of each of the switches 2411 to 241n being connected to each other and the switches 2421 to 242n are connected to the positive line 27 with all of one terminal of each of the switches 2421 to 242n being connected to each other. Moreover, a connecting point between the switch 2411 and the switch 2421 is connected to a first scanning electrode 31 of scanning electrodes 3 (31-3n) Of the PDP 1 (as shown in FIG. 14). As shown in FIGS. 16 and 17, a connecting point between the switch 2412 and the switch 2422 is connected to a second scanning electrode 32 of scanning electrodes 3(31-3n). A connecting point between the switch 2413 and the switch 2423 is connected to a third scanning electrode 33 of scanning electrodes 3(31-3n). Similarly, a connecting point between the switch 241n and the switch 242n is connected to an n-th scanning electrode 3n. Each of the switches 2411 to 241n is turned ON/OFF in response to each of the scanning pulse control signals SSPD11 to SSPD1n to be fed from the controller 22. Each of the switches 2431 to 243n is turned ON/OFF in response to each of the scanning pulse control signals SSPD21 to SSPDn to be fed from the controller 22. Then, each of the switches 2411 to 241n and the switches 2421 to 242n feeds each of the pulses PSC1 to PSCn each having a predetermined waveform sequentially to each of the scanning electrodes 31 to 3n of the PDP 1.
The sustaining driver 25, as shown in FIG. 18, is made up of three pieces of switches 251 to 253. One terminal of the switch 251 is supplied with the sustaining voltage Vs and another terminal of the switch 251 is connected to all the sustaining electrodes 41 to 4n of the PDP 1. One terminal of the switch 252 is connected to all the sustaining electrodes 41 to 4n of the PDP 1 and another terminal of the switch 252 is connected to a ground. One terminal of the switch 253 is supplied with the bias voltage Vsw and another terminal of the switch 253 is connected to all the sustaining electrodes 41 to 4n. Each of the switches 251 to 253 is turned ON/OFF in response to the sustaining driver control signals SSUD1 to SSUD3 and feeds a sustaining pulse PSU having a predetermines waveform to all the sustaining electrodes 41 to 4n (shown in FIG. 16)of the PDP 1 in response to each of the sustaining driver control signals SSUD1 to SSUD3.
The data driver 26, as shown in FIG. 19, includes m pieces of switches 2611 to 261m, m pieces of switches 2621 to 262m, m pieces of diodes 2631 to 263m and m pieces of diodes 2641 to 264m. Each of the diodes 2631 to 263m is connected in parallel to both ends of each of corresponding switches 2611 to 261m. Each of the diodes 2641 to 244m is connected in parallel to both ends of each of corresponding switches 2621 to 262m. The switch 2611 is daisy-chained to the switch 2621. The switch 2612 (not shown) is daisy-chained to the switch 2622 (not shown). The switch 2613 (not shown) is daisy-chained to the switch 2623. The switch 261m is daisy-chained to the switch 262m. The switches 2611 to 261m are connected to a ground with all of one terminal of each 2611 to 261m being connected to each other and the switches 2621 to 262m are supplied with the data voltage Vd with all of one terminal of each of the switches 262l to 261m being connected to each other. Moreover, a connecting point between the switch 2611 and the switch 2621 is connected to a first data electrode 101 (FIG. 16) of data electrodes 10 (101-10m) of the PDP 1. A connecting point between the switch 2612 and the switch 2622 is connected to a second data electrode 102 of data electrodes 10 (101-10m). A connecting point between the switch 2613 and the switch 2623 is connected to a third data electrode 103 of data electrodes 10 (101-10m). Similarly, a connecting point between the switch 261m and the switch 262m is connected to the mth data electrode 10m (FIG. 16) of data electrodes 10 (101-10m). Each of the switches 2611 to 261m is turned ON/OFF in response to each of the data driver control signals SDD11 to SDD1m to be fed from the controller 22. Each of the switches 2621 to 262m is turned ON/OFF in response to each of the data driver control signals SDD21 to SDD2m to be fed from the controller 22 (FIG. 16). Then, each of the switches 2611 to 261m and the switches 2621 to 262m feeds each of the pulses PD1 to PDm each having a predetermined waveform sequentially to each of the data electrodes 101 to 10m of the PDP 1. Each of the above switches 231 to 236, 2411, to 241m 2421 to 242m, 251 to 253, 2611 to 261m and 2621 to 262m is turned ON while the fed control signal is high and OFF while the fed control signal is low. Instead of these switches, not only physical switches but also switching elements such as a bipolar transistor, field effect transistor or a like can be used.
Next, operations performed immediately after a supply of power-ON the driving circuit of the PDP 1 will be described by referring to a timing chart shown in FIG. 20. In the PDP 1, since luminance of each color of light emitted by each of the display cells is proportional to the number of light emitting pulses, gray-scale display can be produced by changing the number of light emitting pulses in one frame period during which a frame F making up one screen is displayed. To achieve this, one period for the frame F is so configured as to be made up of a plurality of subfield periods SF and binary images are displayed during each of the subfield periods SF and a weight is assigned to light emitting time of each of the display cells for every subfield period SF. Such the method for producing the gray-scale display is called a xe2x80x9csubfield methodxe2x80x9d. FIG. 20 shows a waveform of each of signals fed during a first subfield period SF immediately after the supply of power. However, amplitudes of the pulse Psck (k is a natural number and 1xe2x89xa6kxe2x89xa6n), shown in (1) in FIG. 20, to be fed to a scanning side and the sustaining pulse PSU fed to the scanning side shown in (2) in FIG. 20 are determined in a relative manner and, since states of these signals are ones obtained immediately after the power-ON, voltage values of the sustaining voltage Vs, priming voltage Vp, and bias voltage Vsw are transitory ones which have not yet reached predetermined values. The above subfield period SF includes a priming period Tp which is a period required for causing feeble discharge to occur in order to reduce an amount of wall charges being deposited on both the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n) (FIG. 14) after priming discharge has occurred, an address period TA which is a period required for selecting the display cell used for light emitting, a sustaining period Ts which is a period required for causing the selected display cell to emit light, an electric charge erasing period TE which is a period required for erasing wall charges being deposited on the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n) of the selected display cell during the sustaining period Ts.
As shown in FIG. 16, when power is turned ON, the driving power source 21 first starts feeding the logic voltage Vdd to the controller 22. Then, as shown in FIG. 20, the controller 22, after having initialized its internal circuits, produces, based on the video signal Sv to be fed from an outside, the scanning driver control signals SSCD1 to SSCD6 shown in (3) to (8) in FIG. 20, the sustaining driver control signals SSUD1 to SSU3 shown in (9) to (11) in FIG. 20, the scanning pulse driver control signals SSPD11 to SSPD2n shown in (12) to (17) in FIG. 20, the high-level data driver control signals SDD11 to SDD1m (not shown) used to cause a black color to be displayed on the entire PDP 1 and the low-level data driver control signals SDD21 to SDD2m (not shown) used also to cause the black color to be displayed on the entire of the PDP 1 and then starts feeding each of the corresponding control signals to each of the scanning driver 23, sustaining driver 25, scanning pulse driver 24, and data driver 26.
Next, the driving power source 21, when a few hundred milliseconds have elapsed after having started feeding the logic voltage Vdd to the controller 22, begins feeding the sustaining voltage Vs, priming voltage Vp, scanning base voltage Vbw, bias voltage Vsw and data voltage Vd to each of the scanning driver 23, sustaining driver 25 and data driver 26. As a result, during the priming period Tp, since the switch 231 of the scanning driver 23 is turned ON (see FIG. 17) in response to the scanning driver control signal SSCD1 (see (3) in FIG. 20) and the switch 252 of the sustaining driver 25 is turned ON (see FIG. 18) in response to the high-level sustaining driver control signal SSUD2 (see (10) in FIG. 20), a priming pulse PPRP of positive polarity is applied to all scanning electrodes 31 to 3n and a priming pulse PPRN of negative polarity (see (2) in FIG. 20) is applied to all sustaining electrodes 41 to 4n (FIG. 15). Therefore, the priming discharge occurs in the discharging gas space 14 (FIG. 15) in the vicinity of a gap between the scanning electrodes 31 to 3n and the sustaining electrodes 41 to 4n, which causes active particles inducing easy occurrence of discharging in the display cell to be produced and causes wall charges of negative polarity to be accumulated on the scanning electrodes 31 to 3n and wall charges of positive polarity to be also accumulated on the sustaining electrodes 41 to 4n.
Then, when the sustaining driver control signal SSUD2 (see (10) in FIG. 20) becomes a high to a low, the switch 252 of the sustaining driver 25 is turned OFF and when the sustaining driver control signal SSUD1 (see (9) in FIG. 20) becomes a low to a high, the switch 251 of the sustaining driver 25 is turned ON (see FIG. 18). Then, since the switch 233 of the scanning driver 23 is turned ON (see FIG. 17) in response to the high-level scanning driver control signal SSCD3 (see (5) in FIG. 20), after the voltage of all the sustaining electrodes 41 to 4n is maintained at about 180 Volts, a first charge erasing pulse PEEN1 (see (1) in FIG. 20) is applied to all the scanning electrodes 31 to 3n of negative polarity. As a result, feeble discharge occurs in all the display cells, which causes wall charges of negative polarity on the scanning electrodes 31 to 3n and wall charges of positive polarity on the sustaining electrodes 41 to 4n to be completely erased.
Next, during the address period TA, since the switch 253 of the sustaining driver 25 is turned ON (see FIG. 18) in response to the high-level sustaining driver control signal SSUD3 (see (11) in FIG. 20) and, at the same time, the switches 234 and 235 are turned ON (see FIG. 17) in response to the scanning driver control signal SSCD4 and SSCD5, (see (6) and (7) in FIG. 20) being supplied from a latter half of the priming period Tp, the bias pulse PEP of positive polarity is applied to all the sustaining electrodes 41 to 4n (see (2) in FIG. 20) and the voltage of the pulses Psc1 to PSCn to be applied to all the scanning electrodes 31 to 3n is maintained at the scanning base voltage Vbw, as shown in (1) in FIG. 20).
In such a state as described above, in order to perform writing to each of the display cells in every line, the switches 2411 to 241n of the scanning pulse driver 24 are sequentially turned OFF and the switches 2421 to 242n are sequentially turned ON (see FIG. 17) in response to the low-level scanning pulse driver control signals SSPD11 to SSPD1n and the high-level scanning pulse driver control signals SSPD21 to SSPD2n being fed with timing shown in (12) to (17) in FIG. 20. Moreover, though not shown, the switches 2611 to 261n of the data driver 26 are sequentially turned ON and the switches 2621 to 262n are sequentially turned OFF (see FIG. 19) in response to the high-level data driver control signals SDD11 to SDD1m and the low-level data driver control signals SDD21 to SDD2m, all of which are used to display a black color on the PDP 1, to be fed with the same timing with which the corresponding scanning pulse driver control signals SSPD11 to SSPDin and SSPD21 to SSPD2n are supplied. Therefore, though a writing scanning pulse PWSN is applied to the scanning electrodes 31 to 3n in a line on which the writing is performed, for example, to the scanning electrode 3K as shown in (1) in FIG. 20, since a data pulse of positive polarity is not applied to any data electrodes 101 to 10m, neither facing discharge nor surface discharge as writing discharge between the scanning electrode 3 (31-3n) and the sustaining electrode 4 (41-4n) to be triggered by the facing discharge occurs in any display cell. Therefore, an amount of the wall charges accumulated on the scanning electrodes 31 to 3n and sustaining electrodes 41 to 4n making up all the display cells is very small because there is left only the wall charge accumulated after the wall charge was erased in response to the first charge erasing pulse PEEN1 of negative polarity.
Next, during the sustaining period TS, since the switches 232 and 236 of the scanning driver 23 are turned ON/OFF (see FIG. 17) two or more times alternately in response to the scanning driver control signals SSCD2 to SSCD6 to be fed with timing shown in (4) and (8) in FIG. 20 and, at the same time, the switches 251 and 252 of the sustaining driver 25 are turned ON/OFF (see FIG. 18) two or more times alternately in response to the sustaining driver control signals SSUD1 to SSUD2 to be fed with timing shown in (9) and (10) in FIG. 20. Therefore, as shown in (1) in FIG. 20, a sustaining pulse PSUN1 is applied two or more times to all the scanning electrodes 31 to 3n and a sustaining pulse PSUN2 of negative polarity is applied two or more to all the sustaining electrodes 41 to 4n. However, during the address period TA, since no writing is performed on all the display cells, the amount of wall charges accumulated on the scanning electrodes 31 to 3n and sustaining electrodes 41 to 4n making up all the display cells are very small and, as a result, no sustaining discharge caused by superimposing of a voltage of the sustaining pulse PSUN1 or PSUN2 of negative polarity on a voltage of the wall charge occurs and the display cell does not emit light accordingly.
Next, during the electric charge erasing period TE, since the switch 233 of the scanning driver 23 is turned ON (see FIG. 17) in response to the high-level scanning driver control signal SSCD3 (see (5) in FIG. 20), a second charge erasing pulse PEEN2 of negative polarity shown in (1) in FIG. 20 is applied to all the scanning electrodes 31 to 3n. Therefore, feeble discharge occurs in all the display cells and, as a result, the wall charges of negative polarity accumulated on the scanning electrodes 31 to 3n and the wall charges of positive polarity accumulated on the sustaining electrode 41 to 4n making up the display cell that had emitting light during the sustaining period Ts are completely erased and a state of the charge in the display cells making up the PDP 1 is made uniform.
The conventional driving circuit of the PDP 1, immediately after power is turned ON, operates on a precondition that, when the power is turned ON, electric charges have not been accumulated on the scanning electrode 3 (31-3n), sustaining electrode 4 (41-4n) and data electrode 10 (101-10m) making up each of the display cells. However, in reality, for example, as shown in FIG. 21A, some electric charges reside on the scanning electrode 3 (31-3n), sustaining electrode 4 (41-4n), and data electrode 10 (101-10m) making up some of the display cells. In the example shown in FIG. 21A, electric charges being equivalent to xe2x88x9250 Volts of negative polarity reside on the scanning electrode 3 (31-3n), electric charges being equivalent to 30 Volts of positive polarity reside on the sustaining electrode 4 (41-4n) and electric charges being equivalent to 30 Volts of positive polarity reside on the data electrode 10 (101-10m). In this case, a potential difference in the wall charges between the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n) being adjacent to each other is xe2x88x9280 Volts. Such the residual wall charges are produced mainly due to differences in time taken when each of the priming voltage Vp, sustaining voltage Vs and scanning base voltage Vbw applied to the scanning driver 23, sustaining voltage Vs and bias voltage Vsw applied to the sustaining driver 25 and data voltage Vd applied to the data driver 26, which had been fed from the driving power source 21, drops from a predetermined level to 0 Volts at a time when the power is turned OFF in the driving circuit of the PDP 1 and, therefore, it is almost impossible to completely erase the above residual wall charges at the time when the power is turned OFF.
Therefore, during the above address period TA, in the state where the difference in voltage, caused by the residual wall charges, between the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n) being adjacent to each other is xe2x88x9280 Volts, since the bias pulse PBP of about 195 Volts of positive polarity is applied to all the sustaining electrodes 41 to 4n and since the writing scanning pulse PWSN of 0 Volts of negative polarity is applied to the scanning electrode 3 (31-3n) in a line on which the writing is performed, a voltage of 275 Volts in total is applied between the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n). If a discharge starting voltage is 220 Volts, though the high-level data driver control signals SDD11 to SDD1M and the low-level data driver control signals SDD21 to SDD2m are fed to the data driver 26 in order to cause a black color to be displayed on the entire PDP 1, surface discharge occurs between the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n) as shown in FIG. 21B and, as a result, wall charges of positive polarity are accumulated, which act to counter voltages being already applied, on the scanning electrode 3 (31-3n) making up the display cell in which the surface discharge has occurred and wall charges of negative polarity are accumulated, which also act to counter voltages being already applied, on the sustaining electrode 4 (41-4n) making up the display cell in which the surface discharge has occurred (see FIG. 21C). In the example shown in FIG. 21C, a voltage of 60 Volts of positive polarity is accumulated on the scanning electrode 3 (31-3n) and a voltage of xe2x88x9260 Volts of negative polarity is accumulated on the sustaining electrode 4 (41-4n).
Next, during the sustaining period Ts, in the display cell in which the surface discharge has occurred during the above address period TA, since the wall charges of positive polarity are accumulated on the scanning electrode 3 (31-3n) making up the display cell and the wall charges are accumulated on the sustaining electrode 4 (41-4n) also making up the display cell, the sustaining pulse PSUN1 of 180 Volts of positive polarity is applied to all the scanning electrodes 31 to 3n and, when the sustaining pulse PSUN1 of 0 Volts of negative polarity is applied to all the sustaining electrodes 41 to 4n, since the applied sustaining pulse PSUN2 is superimposed on the wall charges of negative polarity being accumulated on the sustaining electrode 4 (41-4n), a total of 300 Volts being a sum of the difference (120 Volts) produced by the wall charges between the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n) and the difference (180 Volts) in the applied voltage between the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n) is applied between the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n) Therefore, as shown in FIG. 21C, the surface discharge occurs between the scanning electrode 3 (31-3n) and sustaining electrode 4 (41-4n). As a result, the wall charges of negative polarity are accumulated, which act to counter the applied voltage, on the scanning electrode 3 (31-3n) making up the display cell in which the surface discharge has occurred and the wall charges of positive polarity are accumulated, which act to counter the applied voltage, on the sustaining electrode 4 (41-4n) making up the display cell in which the surface discharge has occurred. Thereafter, same operations as above are repeated, which cause the display cell to erroneously emit light and a useless display to be produced in the PDP 1. This phenomenon occurs due to following reasons.
That is, originally, the residual wall charges ought to be erased together at the same time when the wall charges accumulated on the scanning electrodes 31 to 3n and sustaining electrodes 41 to 4n based on the priming discharge occurred in a first half of the priming period Tp are erased by the first charge erasing pulse PEEN1 in the latter half of the priming period Tp. However, since the driving power source 21 causes both the sustaining voltage VS and bias voltage VSW to rise at almost the same time, the sustaining voltage VS does not fully reach a predetermined voltage in the latter half of the priming period Tp occurring, in terms of time, before the address period TA and, as a result, the above residual wall charges cannot be completely erased. Nevertheless, there is a case where the bias voltage VSW has reached the predetermined voltage value and, in this case, the surface discharge occurs easily.
To solve this problem, a method is disclosed in, for example, Japanese Patent No. 2823126 in which image display in the PDP 1 is prohibited during at least one period of a vertical sync signal after power is turned ON. However, in this method, though the image display is merely and mechanically prohibited during at least one period of the vertical sync signal after the power has been turned ON, no consideration is given to a characteristic of the PDP 1 or its driving circuit, in particular to a rising characteristic, to be observed at the time when the power is turned ON, of the sustaining voltage VS to be fed from the driving power source 21, priming voltage Vp, scanning base voltage Vbw and bias voltage Vsw. Therefore, even by using the disclosed method, it is impossible to completely prevent the useless display occurring at the time when the power is turned ON.
This requires strict specifications of characteristics of the driving power source 21 so as to meet conditions defined by the characteristic of operations of the PDP 1 or its driving circuit, however, in that case, the driving power source 21 has to be prepared individually for every PDP 1 or its driving circuit, which causes a loss of general versatility of the driving power source 21. Moreover, since there is a likelihood that the rising characteristics of the sustaining voltage Vs, priming voltage Vp, and scanning base voltage Vbw at the time of the power-ON are changed not only by the single characteristic of the driving power source 21 but also by capacitance of capacitors making up smoothing circuits being connected to the driving power source 21 or parasitic capacitance produced by routing of wirings, unless considerations are given to these factors, it is impossible to achieve a complete prevention of the useless display appearing when the power is turned ON.
In view of the above, it is an object of the present invention to provide a method and a circuit for driving a PDP, and a plasma display device having the driving circuit which are capable of preventing a useless display occurring at a time of power-ON, irrespective of characteristics of a driving power source.
According to a first aspect of the present invention, there is provided a method for driving a plasma display panel, the plasma display panel including a plurality of pairs of surface discharge electrodes each pair of the surface discharge electrodes being made up of a scanning electrode and a sustaining electrode and each scanning electrode and sustaining electrode being formed successively in a column direction and being parallel to a row direction and a plurality of data electrodes each being formed successively in the row direction and being parallel to a column direction, forming pixels at intersections of the plurality of the data electrodes and the plurality of the pairs of surface discharge electrodes, and discharge space existing in a gap between a plane on which the plurality of the pairs of surface discharge electrodes is formed and a plane on which the plurality of the data electrodes is formed, including:
a step of applying, immediately after power is turned ON, a pulse having an erasing pulse which causes a maximum potential difference between the sustaining electrode and the scanning electrode being adjacent to each other to reach at least a sustaining voltage, to the scanning electrode.
In the foregoing, a preferable mode is one wherein, after power is turned ON, the pulse having the erasing pulse is applied repeatedly to the scanning electrode until the sustaining voltage reaches a predetermined voltage value.
Also, a preferable mode is one, wherein, after power is turned ON, the pulse having the erasing pulse is applied to the scanning electrode repeatedly for predetermined time.
Also, a preferable mode is one wherein, the pulse having the erasing pulse and being applied to the scanning electrode has a priming period, address period, and sustaining period; and wherein the erasing pulse is produced during the priming period.
Also, a preferable mode is one wherein, the pulse having the erasing pulse and being applied to the scanning electrode has a first priming period, second priming period, address period, and sustaining period, and wherein the erasing pulse is fed during the first priming period and is made up of a priming pulse which causes a maximum potential difference between the scanning electrode and the sustaining electrode being adjacent to each other to reach at least priming voltage in order to cause priming discharge to occur during the second priming period and of a second erasing pulse used to reduce wall charges accumulated both on the scanning electrode and sustaining electrode being adjacent to each other caused by the priming discharge.
Also, a preferable mode is one wherein, after the pulse having the erasing pulse has been applied, a pulse having a priming period and address period and having a writing scanning pulse which causes a potential difference between the scanning electrode and the sustaining electrode being adjacent to each other during the address period to become a sustaining voltage, is applied during the address period to the scanning electrode.
According to a second aspect of the present invention, there is provided a circuit for driving a plasma display panel, the plasma display panel having a plurality of pairs of surface discharge electrodes each pair of the surface discharge electrodes being made up of a scanning electrode and a sustaining electrode and each scanning electrode and sustaining electrode being formed successively in a column direction and being parallel to a row direction and a plurality of data electrodes each being formed successively in the row direction and being parallel to the column direction, forming pixels at intersections of the plurality of the data electrodes and the plurality of the pairs of surface discharge electrodes, and discharge space existing in a gap between a plane on which the plurality of the pairs of surface discharge electrodes is formed and a plane on which the plurality of the data electrodes is formed, including:
a controller to produce, immediately after power is turned ON, a control signal used to apply a pulse having an erasing pulse which causes a maximum potential difference between the sustaining electrode and the scanning electrode being adjacent to each other to reach at least a sustaining voltage, to the scanning electrode.
In the foregoing, a preferable mode is one that wherein includes:
a voltage detection circuit to detect, after power is turned ON, the sustaining voltage which has reached a predetermined voltage; and
wherein the controller produces the control signal repeatedly until the voltage detection circuit detects the sustaining voltage that has reached a predetermined voltage value.
Also, a preferable mode is one that wherein includes a timer to measure predetermined time after power is turned ON and wherein the controller produces the control signal repeatedly until the timer has measured the predetermined time.
Also, a preferable mode is one wherein the pulse having the erasing pulse and being applied to the scanning electrode has a priming period, address period and sustaining period; and wherein the erasing pulse is produced in the priming period.
Also, a preferable mode is one wherein, the pulse having the erasing pulse and being applied to the scanning electrode has a first priming period, second priming period, address period, and sustaining period, and wherein the erasing pulse is fed during the first priming period and is made up of a priming pulse which causes a maximum potential difference between the scanning electrode and the sustaining electrode being adjacent to each other to reach at least a priming voltage in order to cause priming discharge to occur during the second priming period and of a second erasing pulse used to reduce wall charges on the scanning electrode and sustaining electrode being adjacent to each other caused by the priming discharge.
Also, a preferable mode is one wherein the controller, after applying the pulse having the erasing pulse, produces a control signal having a priming period and address period and writing scanning pulse to cause a potential difference between the scanning electrode and the sustaining electrode being adjacent to each other to become a sustaining voltage during the address period.
According to a third aspect of the present invention, there is provided a plasma display device being provided with a driving circuit of a plasma display stated in any one of the second aspect.
According to a fourth aspect of the present invention, there is provided a plasma display panel device being equipped with a controller which produces a control signal used to apply, immediately after power is turned ON, a pulse having an erasing pulse causing a maximum potential difference between a scanning electrode and a sustaining electrode being adjacent to each other to reach a sustaining voltage to the scanning electrode.
With above configurations, a pulse having an erasing pulse which causes a maximum potential difference between a sustaining electrode and a scanning electrode being adjacent to each other to reach at least a sustaining voltage, is applied, immediately after power is applied, to the scanning electrode and therefore a useless display can be prevented at a time of power-ON, irrespective of characteristics of the driving power source.